(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices on semiconductor substrates, and more particularly relates to a method for making reliable low-resistance silicide contacts between closely spaced patterned conducting stripes, hereafter also referred to as conducting lines. The method is particularly applicable for making more reliable silicide (source/drain) contacts between closely spaced sub-quarter-micrometer polysilicon gate electrodes (=or less than 0.25 um) for FETs. An ion implantation is used to amorphize any remaining residual silicon oxide (SiO2) between the polysilicon gate electrodes during formation of sidewall spacers. The amorphized oxide is then more rapidly removed in a wet etch, avoiding overetching that would cause device degradation.
(2) Description of the Prior Art
Advances in the semiconductor process technologies in recent years have dramatically decreased the device feature sizes and increased the circuit density on integrated circuit chips. Current circuit densities require conducting lines having sub-quarter-micrometer widths ( less than 0.25 um) with spacings that can be 0.35 um or less in width. One structure where these narrow spacings can occur is between the closely spaced polysilicon gate electrodes used to make the field effect transistors (FETS) with sub-quarter-micrometer channel lengths for Ultra Large Scale Integration (ULSI) circuits.
The conventional PETs are typically fabricated by patterning polysilicon gate electrodes over a thin gate oxide over device areas on a single-crystal semiconductor substrate. The gate electrode structure is used as a diffusion or implant barrier mask to form self-aligned lightly doped source/drain areas in the substrate adjacent to the sides of the gate electrodes. Next a conformal insulating layer is deposited and anisotropically etched back to form insulating sidewall spacers on the sides of the gate electrodes. Heavily doped source/drain contact areas are formed next to the sidewall spacers to complete the FET.
Unfortunately, when the conformal insulating layer, typically SiO2, is etched back, the plasma etch rate is slower between the closely spaced gate electrodes, which makes it difficult to form reliable low-resistance ohmic contacts to the source/drain contact areas. The slower etch rate is believed to be a result of the depletion of the etchant gas in the high-aspect-ratio spaces between the gate electrodes. This etching problem is best understood by referring to the prior art FIG. 1. As shown in FIG. 1, the gate oxide 12 is formed on the substrate 10 and a poly-silicon layer 14 is deposited and patterned to form the closely spaced gate electrodes, also labeled 14. Lightly doped source/drain areas 17(Nxe2x88x92) are formed adjacent to the gate electrodes. A conformal insulating layer 16 is deposited and anisotropically plasma etched back to form the sidewall spacers 16 on the gate electrodes. However, during the plasma etching, the slower etch rate results in residual portions 16xe2x80x2 of the insulating layer 16 remaining between the closely spaced gate electrodes. The heavily doped source/drain contact areas 19(N+) are formed next by implanting a dopant. However, this oxide residue 16xe2x80x2 makes it difficult to form good ohmic contacts to the source/drain contact areas 19(N+). Typically the residual oxide 16xe2x80x2 is removed by using an extended wet etch in a hydrofluoric (HF) acid solution, which can result in higher leakage currents and degrade the device characteristics.
Several methods for making FET gate electrodes have been described in the literature. For example, in U.S. Pat. No. 5,731,239 to Wong et al. a method is described for making low-sheet-resistance gate electrodes by amorphization using ion implantation, while avoiding implant damage in the source/drain areas. In U.S. Pat. No. 5,656,546 to Chen et al. a method is described for implanting nitrogen into titanium silicide contacts to reduce the sheet resistance, U.S. Pat. No. 5,869,359 to Prabhakar describes a method for making FETs with raised source/drain areas on a silicon-on-insulator structure. Byun in U.S. Pat. No. 5,607,884 describes a method for making FETs with source/drain regions having shallow diffused junctions with thin silicide contacts. U.S. Pat. No. 5,866,451 to Yoo et al. describes a method for making semiconductor devices having 4T static RAMS and mixed-mode capacitors in logic, but the invention does not address the residual silicon oxide between closely spaced gate electrodes. Huang in U.S. Pat. No. 5,863,820 describes a method for making salicide contacts and self-aligned contacts on the same chip. However, none of the above references addresses the problems associated with residual silicon oxide between closely spaced gate electrodes resulting from slower etching in high-aspect openings, as described above.
Therefore, there is still a strong need in the semiconductor industry for making reliable closely spaced sub-quarter-micrometer gate electrodes having low-resistance silicide contacts to the FET source/drain contact areas without requiring excessive HF wet etching that would otherwise degrade device performance.
It is therefore a principal object of this invention to form reliable low-resistance silicide contacts to a silicon substrate between closely spaced patterned electrically conducting lines having insulating sidewall spacers, and more particularly relates to forming low-resistance silicide contacts to source/drain contact areas between polysilicon FET gate electrodes.
Another object of this invention is to provide these more reliable low-resistance silicide contacts by ion implanting to amorphize the unwanted residual SiO2 between the gate electrodes that remains after insulating sidewall spacers are formed, making the amorphized oxide easier to remove (more rapid removal) in a wet etch.
A further object of this invention is to amorphize the SiO2 by using a low-energy ion implant of nitrogen or germanium, which damages or degrades the oxide and results in a higher etch rate, without increasing device leakage current.
Still another objective of this invention is to improve the silicide/silicon substrate interface and to amorphize the top surface of the polysilicon gate electrodes to reduce junction leakage current by making a smoother silicide/silicon substrate interface, and to reduce the sheet resistance of the polycide gate electrodes.
In accordance with the objects of this embodiment, a method is provided for making improved low-resistance silicide contacts between closely spaced electrically conducting lines by removing the residual oxide remaining after anisotropic plasma etching, as described in the prior art. The method is particularly useful for making silicide contacts to source/drain contact areas between closely spaced field effect transistor (YET) gate electrodes.
The method begins by providing a semiconductor substrate. The substrate is typically a conductively doped single-crystal silicon. The FETs are formed in device areas that are typically surrounded and electrically isolated by field oxide regions. A thermal oxide is formed on the device areas to provide a thin gate oxide for the PETs. A conducting layer, preferably a conductively doped polysilicon layer, is deposited on the substrate, and the polysilicon layer is then patterned by photoresist masking and anisotropic etching to form closely spaced gate electrodes on the device areas and to form electrically interconnecting lines over the field oxide. Lightly doped source/drain regions are formed adjacent to the gate electrodes by implanting ions, such as As75. Insulating sidewall spacers are formed on the sidewalls of the gate electrodes by depositing a conformal insulating layer over the gate electrodes and anisotropically etching back the insulating layer. Unfortunately in the conventional plasma etching process, the etch rate is slower between closely spaced lines because of the depletion effect of the etchant gas. This slower etch rate results in residual SiO2 that makes it difficult to form good low-resistance ohmic silicide contacts for the FETs. Next, heavily doped source/drain contact areas are formed adjacent to the sidewall spacers by implanting a dopant.
A key feature of the invention is to perform an additional ion implant to amorphize the residual SiO2. For example, the SiO2 can be implanted with nitrogen or germanium ions to damage or degrade the residual oxide and to increase the wet etch rate. A wet etching is used to completely remove the residual SiO2, which has a higher etch rate, without overetching other portions of the SiO2 sidewall spacers. Silicide contacts are now formed by depositing a metal layer, such as cobalt (Co), titanium (Ti), or nickel (Ni). The metal layer is annealed to form silicide contacts on the source/drain areas of the substrate between the closely spaced polysilicon gate electrodes. The annealing also forms a silicide on the top surface of the exposed polysilicon gate electrodes. The unreacted portions of the metal over the SiO2 surfaces are completely removed by etching. This result in self-aligned silicide (salicide) FET structures having good silicide contacts. The ion implant to amorphize the SiO2 carried out prior to forming the silicide also modifies the top surface of the substrate to provide a smoother silicide/silicon substrate interface, which further reduces junction leakage current. The amorphizing implant also modifies the top surface of the polysilicon gate electrodes, which reduces the sheet resistance when the silicide is formed on the gate electrodes.